Variable duty cycle switching with imposed delay

ABSTRACT

Power conversion methods, systems, articles of manufacture, and devices are provided. The power conversion may include converting between direct current and alternating current wherein switching losses associated with latent electrical charges are reduced. Current sensing may be low-side bus reference. Solid-state implementations, code implementations, and mixed implementations are provided.

BACKGROUND

The present invention relates to solid-state power conversion and morespecifically to solid-state switch management, feedback, and control.

An inverter is an electrical device that uses switches to convert directcurrent into alternating current. The switches open and close in apattern to create a reciprocating current back and forth through a load.Conditioning and other circuit functionality can be applied to theresulting reciprocating current to change or manage its frequency,voltage, and size. Switches in inverters may be both mechanical andsolid-state.

Devices performing the converse function of inverters are calledrectifiers. Rectifiers function to convert an alternating current into adirect current. Like inverters, rectifiers may use switches that openand close in a pattern to create a single polarity current through aload. Also like inverters, rectifiers may be both mechanical andsolid-state.

Solid-state inverters and rectifiers may use electronic switches,including FETs and MOSFETs, to convert direct current into alternatingcurrent or alternating current into direct current. Solid-stateinverters may be employed to provide AC power from DC sources such assolar panels, batteries, and fuel cells while solid-state rectifiers maybe used to convert alternating current from a power grid or AC generatorinto direct current for use to charge batteries, driving DC motors, orpowering other DC current loads.

As with all power management systems, conversion losses in bothinverters and rectifiers can serve to reduce the amount of poweravailable after the power has been converted to a useable form. Thesmaller the quantity of the loss the more efficient the inverter orrectifier is considered to be. Power losses may be attributable toswitching attributes, including the buildup of electric charge in acircuit, and the opposition to current an electric charge buildup mayprovide.

Switches in solid-state inverters can be positioned in a two-by-twoconfiguration, commonly referred to as an H-bridge. In thisconfiguration pairs of switches can fire to create alternating currentthrough the load.

Embodiments provided herein are directed to, among other things,inverters, rectifiers, switch topologies for power conversion, currentconditioning, voltage conditioning, current and voltage sensing, switchfeedback, switch timing, and switch topology. Other embodiments may beplausible as well.

BRIEF SUMMARY

Embodiments may include processes, machines, and articles ofmanufacture. These embodiments may serve to provide switch operationhaving reduced switching losses or improved signal output, or both.Embodiments may include the use of upper and lower duty cycle boundariesto manage the operation and timing of switching operations. Inembodiments, these duty cycle boundaries may be constants or variableand may be offset as well. Switching losses may be controlled or managedthrough the use of these duty cycle boundaries.

Embodiments may further include switch-side current sensing and logicalcurrent sensing for feedback control. Still further, embodiments mayalso include secondary global feedback control. These and otherembodiments are described throughout and should be seen as exemplary andnot limiting on the scope of invention.

Embodiments may include solid-state circuits having power train switchesand diodes, sensor circuits configured to provide a sensor signalindicative of current flowing from the power train switches, and a logiccircuit electrically coupled to the power train switching circuit, thelogic circuit configured to send switching instructions for switchingswitches in the power train switching circuit. These switchinginstructions may include switching a pair of switches on and off,independently switching a third switch in the power train on and off,and holding open a fourth switch in the power train. In embodiments, theswitches may have various configurations including MOSFET transistors,IGBT transistors, and other configurations as well. In embodiments thediodes may be included within the switches, as with MOSFET transistors,and may be separate as well, as with p-n junction diodes connectedacross IGBTs in an antiparallel configuration.

Embodiments may also include: a power converter having a switching typestep-down converter circuit; having an input port to couple to a supplyvoltage; and having an output port to provide an output voltage at amagnitude that is lower than a magnitude of the supply voltage. Thepower converter may further contain a control circuit to receive afeedback signal and regulate the magnitude of the output voltage inresponse thereto, a switching type DC/AC converter circuit having aprimary side and a secondary side, a rectifier circuit having an inputport and an output port, the input port being coupled to the secondaryside of the DC/AC converter circuit, and a feedback circuit to generatethe feedback signal in response to the output port of the rectifiercircuit.

Embodiments may also include converting direct current to alternatingcurrent. These embodiments may include generating a command signalrepresenting a desired current, sensing an existing current in anH-bridge switch powertrain, comparing the command signal with the sensedcurrent, and generating a first set of switching signals, the setincluding signals to alternately switch a first switch and a secondswitch in the H-bridge powertrain on and off, independently turn a thirdswitch in the H-bridge powertrain on and off, and hold a fourth switchof the H-bridge powertrain open.

Embodiments may include converting alternating current to directcurrent. These conversions may include generating a command signalrepresenting a desired current, sensing an existing current in a switchpowertrain, comparing the command signal with the sensed current, andgenerating a first set of switching signals, the set including signalsto alternately switch a first switch and a second switch in thepowertrain on and off, independently turn a third switch in thepowertrain on and off, and hold a fourth switch of the powertrain open.

According to aspects of embodiments of the invention, a power conversionmay be provided. Embodiments may include: receiving a supply voltage andgenerating a first output voltage having a magnitude that is higher orlower than a magnitude of the supply voltage, where the act ofgenerating comprises regulating the first output voltage in response toa feedback signal; generating an AC voltage from the first outputvoltage or generating a DC voltage from the first output voltage;rectifying the AC voltage to provide a DC voltage or inverting the DCvoltage to provide an AC voltage; and generating a feedback signal inresponse to the generated voltage.

This invention and/or embodiments thereof will be further described andappreciated from the accompanying detailed description in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 shows and H-bridge switching topology of a power circuit as maybe employed in accord with embodiments of the invention.

FIG. 2 shows an alternating current held between top and bottomduty-cycle boundaries as may be employed in accord with embodiments ofthe invention.

FIG. 3 shows power conversion circuitry including top and bottomboundary comparators as may be employed in accord with embodiments ofthe invention.

FIG. 4 shows top and bottom voltage boundaries for an approximateswitching cycle as may be employed in accord with embodiments of theinvention.

FIG. 5 shows a current signal for an approximate switching cycle as maybe rendered in accord with embodiments of the invention.

FIG. 6 shows a current signal for an approximate switching cycle as maybe rendered in accord with embodiments of the invention.

FIG. 7 shows top and bottom voltage boundaries for an approximateswitching cycle as may be employed in accord with embodiments of theinvention.

FIG. 8 shows a current signal for an approximate switching cycle as maybe rendered in accord with embodiments of the invention.

FIG. 9 shows circuitry, including feedback circuitry, as may be employedin accord with embodiments of the invention.

FIG. 10 shows power conversion circuitry using switch side leg sensorresistors as may be employed in accord with embodiments of theinvention.

FIG. 11 shows analog multiplexer circuitry as may also be employed withthe switch side leg sensor resistors in accord with embodiments of theinvention.

FIG. 12 shows a schematic of circuit logic parameters as may be employedin accord with embodiments of the invention.

FIG. 13 provides features as may be individually or cumulativelyemployed in processes in accord with embodiments of the invention.

DETAILED DESCRIPTION

Embodiments of the invention may provide switching, sensing, orfiltering techniques as may be employed by or for power conversioncircuits. These can include the use of solid-state switchingmethodologies to control or assist switching management and timing, aswell as to control or assist circuit feedback and sensing. Embodimentscan include the use of software to control or assist switchingmanagement, switching timing, and circuit feedback and sensing.

These methodologies can include the introduction of fixed or variableduty-cycle boundaries to reduce or eliminate power loss associated withimperfect switching circuits. These methodologies can also include oremploy feedback and filtering circuits to control currents or voltagesbetween or around fixed and variable boundaries and to smooth outputpower signals from power conversion circuits.

Switch circuitry imperfections addressed in embodiments can include, butare not limited to reducing electrical charges, commonly called reverserecovery charges, which can serve to retard current flow. These reverserecovery charges may be formed or serve to impede current flow in p-njunction diodes, including those found in transistor body diodes as wellas diodes used outside of transistors, but in conjunction with them.Different or additional sources and attributes of imperfect switchcircuitry may also be addressed in embodiments. Still further, incertain embodiments, little or no measurable improvement to switchcircuitry imperfections may be accomplished or perceived.

In embodiments, inverter switches may be fired in certain sequences andin certain groups. A result of these methodologies may provide forreduced MOSFET or other switch body diode recovery losses. These timingsequences may include having switches operate in critical conductionmode for prescribed periods of time and at times triggered by hysteresistype feedback and sensing.

Through the use of fixed or variable voltage boundaries, MOSFETs orother switches with antiparallel diodes may be timed and fired such thatbody diode losses or other diode losses associated with reverse currentswitching may be diminished if not eliminated. In other words, switchtiming, switch methodologies, and switch topologies may be used thatprovide dead time for latent electrical charges in antiparallel diodesor other electrical charge impediment to dissipate before switches maybe fired again and currents reversed.

Further to the above, embodiments may provide that current in amonitored powertrain be sensed directly from an inductive filter using asmall resistance or shunt to produce a small voltage proportional to thecurrent. This small voltage, which may be less than 50 mV, may beamplified to several volts in order to improve resolution and noiseimmunity. In embodiments, based on the difference in the measuredcurrent and a commanded current, a duty-cycle command may be produced.This duty-cycle command may be converted to switching signals thatcontrol switching MOSFETs in the power train. And, in embodiments, thiscommand duty-cycle may adjust for or seek to reduce body-diodeconduction loss problems through timing and delay firing methodologies.In so doing, variable and shifted boundaries serving to set the switchtriggering signals may be used.

Still further, in embodiments, modified hysteresis control may also beused. In these embodiments, the sensed current may also be compared to acommanded current. If the sensed current exceeds the commanded currentthen the MOSFETs or other switches may be switched to redirect thecurrent to decrease. Likewise, if the sensed current goes below thecommanded current the MOSFETs or other switches may be switched toredirect the current increase. In so doing the actual current mayoscillate back and forth around the commanded current.

Also, in these hysteresis embodiments, the sensed current may becompared to variable offset boundaries that serve to reduce switchinglosses associated with diode reverse recovery. Here, as well as in otherembodiments, a reduction in switching losses may be realized byintroducing a very short delay of dead time between the commutation ofswitches. This dead time may provide sufficient time for body diodeconduction to dissipate, thereby reducing associated switching losses.Since current in the switches returns to zero or near zero inembodiments, the inverter may be considered to be a critical conductionmode inverter.

FIG. 1 shows a power train topology power circuit 100. Visible in thecircuit of FIG. 1 are MOSFET switches 110, 112, 114, and 116, dc voltagesource 140, inductor 120, inductor current 150, and output/line voltage130. Also visible in FIG. 1 are body diodes 111, 113, 115, and 117.These body diodes are resident within MOSFET switches 110, 112, 114, and116, but are explicitly shown to explain switching methodology ofembodiments described herein.

In embodiments, including FIG. 1, a sensed current may be compared to atarget current in order to control the switches of the power train of acircuit. When the sensed current exceeds the commanded current by somepredetermined amount, the MOSFET switches 110, 112, 114, and 116 may beswitched to redirect the current to decrease its flow. Likewise, if thesensed current goes below the commanded current by the predeterminedamount, the MOSFET switches may be switched to redirect the currentincrease. In this way, the actual current oscillates back and fortharound the commanded current.

In embodiments, this switching methodology may be further defined suchthat when i_(o) 150 is positive, MOSFETs 114 and 112 may switch rapidly,MOSFET 111 may be off, and MOSFET 116 may be held on. More specifically,when MOSFET 114 is on, i_(o) 150 may increase towards a threshold thatis related to the desired output current of the power circuit 100. Whenthis threshold is reached, MOSFET 114 may be turned off and MOSFET 112may be turned on. Subsequent to this switching activity, there may alsobe a very short delay, designated as dead time or deadband between thecommutation of the two switches 112 and 114. During this deadband time,the body diode of MOSFET 112 may turn on as the inductive currentcontinues to flow. Once MOSFET 112 turns on, most or all of the currentmay flow through MOSFET 112 instead of its body diode 113. Also, onceMOSFET 112 is on, the current i_(o) 150 may decrease toward zero. Atzero, there may be little if any current flowing in either MOSFET 112 orits body diode 113. In this way, switching loss experienced by eitherthe MOSFET 112 or the body diode 113 may be reduced.

Conversely, when the current is flowing in the opposite direction, thetiming and activity of the switches may be reversed. For example,MOSFETs 110 and 116 may switch rapidly while MOSFET 114 may be off andMOSFET 112 may be held on. Thus, when MOSFET 110 is on, i_(o) 150 maymove towards a threshold that is related to the desired output currentof the inverter. When this threshold is reached, MOSFET 110 may beturned off and MOSFET 116 may be turned on.

By following this switching methodology, the current may reach zero eachswitching cycle. However the current may not dwell there for asignificant or substantial amount of time.

While remaining at zero may serve to discharge MOSFET body diodes andreduce associated power losses, the output signal may become toodistorted when zero lag times are too long. Likewise, when zero crossingtimes are too short, the output signal may contain less noise, but thepower losses may be more significant. The use of variable duty-cycleboundaries may be used in embodiments when waveform integrity isdesired. The startup noise may be generated when circuit components aresettling in. Distortion, once the circuit is up and running, is notpreferred as it can cause failure to meet standards or other problems.

The power train of FIG. 1, as well as other embodiments, may alsoinclude further filtering to smooth the output power. In a preferredembodiment, the frequency of the switching will be high such thatsmaller inductors may be used in “LCL” and other types of filters.

FIG. 2 shows duty-cycle boundaries as may be employed in embodiments. Ascan be seen the top duty-cycle boundary may be sinusoidal and the bottomduty-cycle boundary may be constant. In FIG. 2, the boundaries have beenshifted by −0.5 A for the bottom boundary and by +0.5 A for the topboundary. The current generated from these boundaries may beapproximately half of the distance between the boundaries. In thisembodiment, as well as in others, the bottom boundary may be offset fromthe 0A axis to reduce switching losses. When this offset is performed,the upper boundary may be offset by a similar amount to maintain powercircuit output.

As can be seen in FIG. 2, with the offset, the top boundary 210 isdefined by the curve 2i*+0.5 and the bottom boundary 220 is defined bythe constant −0.5A. The triangles within the boundaries representthousands of oscillations of current through the inductors. Theseoscillations may be defined by numerous upper and lower boundary curvesand boundary constants. The top boundary may be set so that that topvalue of the current is sinusoidal. The bottom boundary may be set suchthat it provides that the MOSFET body diodes have had adequate time torecover. In embodiments, as noted, the bottom boundary may be offsetfrom zero amps such that adequate time for discharge of the MOSFET bodydiodes is provided. During time in which the current is negative, storedcharge in the MOSFET body diodes may be dissipated. In a negative cycle,the boundaries may reverse, with the top boundary being a constantvalue, perhaps +0.5 amps and the bottom boundary being a sinusoidal andoffset by −0.5 amps. FIG. 4 shows an example of this.

In embodiments, hysteresis control may be used to control commandedcurrent. As noted, the upper bound may be allowed to vary with thecommanded current while the lower bound may be fixed. As shown in FIG.2, for a given cycle, the current may form a triangle from i_(l) toi_(u). For these triangles it can be shown that the average value of thecurrent is

ī=½(i _(u) +i _(l))

where a preferred upper bound (assuming a fixed lower bound) may be setto

i _(u)=2ī−i _(l)

In embodiments the lower bound may be set to 0 A. In this instance, theupper bound may be twice the desired current. In other preferredembodiments, the lower bound may be set slightly below 0 A. By settingthe bound below 0 A, a stored charge in the body diode may have time todissipate before a top switch (e.g., MOSFET 114) is turned on. Inpreferred embodiments, some lower bound near and below 0 A may bepreferred for minimizing overall loss when conduction, switching loss,and body-diode switching loss, are collectively considered.

Varying the boundaries under different circumstances may be preferred inother embodiments and exemplary boundary configurations are addressed infurther detail below.

FIG. 3 illustrates an exemplary power converter with an H-bridge typetopology. The timing of the switching events and the use of currentsensing may employ embodiments. Likewise, the comparator inputs mayexemplify the boundaries described herein and the related and prescribeddiode discharges.

FIG. 3 shows a DC power supply 301 that incorporates a power convertercircuit 300 in accordance with embodiments of the invention. The powerconverter circuit of FIG. 3 may be used by itself, as a power supply, ormay be combined with one or more other circuits in forming other typesof power supply circuits, for example, to provide an AC power supply302. Furthermore, sections of the circuit 300 may also be used inrectifiers embodying the invention.

Circuit 300 can be considered to include several main elements: a DCpower source 301, switches 310, a filter 320, a sensor circuit 330, again circuit 340, a comparator circuit 350, gate drives 375 and 385, andcontrol circuitry consisting of, for example, a flip-flop 360 andcommand gates 370, 380. These main elements may be used to output the ACoutput voltage 302.

FIG. 3 shows the DC power source 301 connected to four power MOSFETswitches 311-314 in an H-bridge configuration. These power MOSFETSinclude body diodes in anti-parallel orientation. The body diodes arenot explicitly illustrated in FIG. 3 but are shown above in FIG. 1.Inductors L1 321, L2 322 and capacitor C1 323 are also shown in FIG. 3.The inductors L1 and L2 and the capacitor C1 may serve to smooth theoutput of the four MOSFET switches, which is inherently rough. In otherwords, the inductors and capacitor may serve as a third-order filterthat dampens the output of the power MOSFETs into a smoother sinewaveform. This smoother sine waveform may be fed to the alternatingcurrent voltage source 302. This voltage source 302 may be considered tobe an AC voltage to the power grid.

In embodiments, the MOSFETS in FIG. 3 may be opened and closed in apattern such that they serve as a pulse-width modulated bridge. Inoperation, depending upon the positions of the MOSFETS, the bridge maybe producing one of three outputs: positive direct current, negativedirect current, and zero direct current. The speed with which theMOSFETS are opened and closed may be increased in certain embodimentssuch that the size of the inductors may be preferably minimized orreduced.

Brief periods may exist where two switches are both carrying the fullcurrent and blocking the full voltage causing a spike of power for,perhaps, nanoseconds. On average, these spikes add up to a significantamount of power loss. Thus, preferred embodiments provide switching fastwithout dissipating much power.

The body diodes of the MOSFETS 311-314 serve to dissipate current fromthe inductor L1 in instances when Q1 311 and Q2 313 are turned off.However, these body diodes may have poor reverse recovery chargecharacteristics. In embodiments, when these body diodes conduct thereverse recovery event may be reduced or eliminated as these reverserecovery events can constitute large portions of switching loses.

The sensing circuit 330 may act to detect the current that is flowingthrough the inductors. In embodiments, the value of R_(s) may be small,perhaps 20 m ohms. As shown, the sensing circuit may also include anop-amp or gain amplifier R_(f) 340, which serves to provide a voltageindicative of the current flowing through the inductors. Two signals,which represent the top and bottom of the voltage, may then be fed tocomparators 351 and 352. Signals B_(b) and B_(t) fed into thesecomparators may represent the boundaries for the top and bottom of thevoltage. When boundaries are crossed, flip flops may be set and reset tomanage the MOSFET switches and the current flowing through theinductors. The signals Q 354 and Q 353 may be used to determine if theflip flops are set or reset.

In FIG. 3 the additional gates show how signals P_(c) and P_(c) , whichrepresent the polarity of the current, may be used to control switchingsignals q₁-q₂ 382 and q₃-q₄ 372. These switching signals 382 and 383 maybe fed to gate drive circuits 385 and 375. So instructed, the gate drivecircuits may then serve to fire the applicable gate node of one or moreof the switches 311-314. When the voltage is positive, P_(c) is set toone and the current P_(c) may be zero. In embodiments, the duty-cycleboundaries may be set such that when the diodes discharge they may do sowithout spiking or without heavy noise anomalies.

FIG. 4 shows top and bottom duty-cycle boundaries for almost an entireswitching cycle. As can be seen the cycle can last less than 0.02seconds and the voltage may be positive and ranging from above 3.5 voltsto below 1.5 volts. These ranges are exemplary and may vary dependingupon the use and particular circuit involved. Here, the voltages havebeen offset such that 2.4 volts represents zero amps.

In embodiments, varying the top boundaries can serve to determine howmuch power is delivered to the grid—with the larger the area under theboundary the more power may be delivered. The bottom boundaries may benear zero amps, but are more likely offset in order to clear out chargein the body diodes or other circuit elements providing reverse recoverycharges. The cycle speed in this and other embodiments may be on theorder to 200 KHz.

FIG. 5 illustrates the current output of a power controller circuitcontrolled consistent with embodiments of the invention. Notably, theboundary parameters from which this current wave was taken employs avariable upper boundary and a fixed lower boundary, such as theboundaries shown in FIG. 4.

Feedback controllers may be employed to provide current outputsconsistent with FIG. 5. These controllers may serve to correct forerrors such as start up noise 510, and for zero-cross distortions 500,both of which are shown in FIG. 5. In addition to using the feedbackcircuit to settle the current, all four switches may be pulsed near thezero-crossing to facilitate pushing through that crossing. This pulsingmay occur 300 microseconds before and after the zero-crossing. Thispulse timing may be selected based upon a percentage of the cycle time.For example, with a 60 Hz cycle waveform, a 300 microsecond lead and lagcan represent about 1.8% of a line cycle. In preferred embodiments, thispulsing may have a small impact on efficiency and may have thebeneficial effect of reducing distortion at the zero-crossing. Inembodiments, the pulsing may occur at different times and for differentdurations as well. Still further, the pre-crossing pulse may begin 200microseconds before zero-crossing and the post-crossing pulse may end350 microseconds after zero-crossing. other pulse times and percentagesof cycle time may be employed as well in embodiments.

FIG. 6 shows the corresponding current for the boundaries of FIG. 4,where the current is oscillating between two boundaries at a rateapproximately equal to 200 KHz. In FIG. 6, an offset of 0.25 A wasemployed and peak current was 1.0 A.

FIG. 7 shows top and bottom boundaries where the bottom boundary has asinusoidal aspect instead of being a constant. In this embodiment thebottom boundary begins and ends at 0.0 and then moves to −0.5 during acycle. By moving off of zero, clearing out the body diode charge may beaccomplished.

As shown in FIG. 7, the top boundary may be defined by the wave

B _(top)=2.4424+2 sin(ωt)P _(c) +O

and the bottom boundary may be defined by the wave

B _(bottom)=2.4424+2 sin(ωt) P _(c) −O

As can be seen, these boundary equations may be shifted by aconstant—here 2.4424. This shift constant may serve to provide thatcurrent sense amplifiers substantially always or always output positivevalues, even when the current becomes negative. Accordingly, inembodiments the output of a current sense amplifier may include the sumof a shift constant and the value of the actual sensed current.

The upper boundary and the lower boundary can serve to have the effectof reducing switching loss by clearing out reverse recovery charges. Inembodiments, variable bottom boundaries may provide for a much smoothertransition from positive current to negative current. A smoothtransition is shown in FIG. 8. Comparatively, because of the largerarea, constant duty-cycle boundaries can serve to ensure that chargesare cleared out more thoroughly than with variable duty-cycleboundaries. This more complete clearing of electrical charge can providefor more efficient switching. Comparatively, variable duty-cycleboundaries may provide for smoother output waveforms but not asefficient switching and associated losses.

Embodiments may also include duty-cycle boundaries setting otherthresholds. These thresholds can include constant stepped boundaries,where the steps increase or decrease in fixed or variable amounts andthe plateaus of the steps may remain constant as well as variablestepped boundaries, where the steps increase or decrease in fixed orvariable amounts and the plateaus of the steps may themselves be curvedor variable. Still further, the steps in these or other embodiments maybe variable and may or may not be uniform. Other modifications to theboundaries, and the thresholds they set, are also possible.

FIG. 8 shows current output where the offset may be adjusted to aconstant value of 0.25 and the output peak current is set to 1 A, whichare the boundaries shown in FIG. 7. As can be seen, zero-crossdistortion 800 and startup distortion 810 may also be adjusted andmanaged by offsets in the values of the boundaries and adjustments inthe peak current settings. Notably, embodiments need not employ feedbackcontrollers to function. The simulation represented in FIG. 8 does notemploy such a controller.

FIG. 9 shows a portion of an exemplary circuit embodying the invention.In FIG. 9, op-amp feedback circuit generates an error signalrepresenting the difference between the desired current and the actualcurrent. Embodiments may or may not include this secondary globalfeedback circuit as the op-amps U5 and U7 also serve to provide feedbackcorrection in the circuit. The Q_(err) signal may then be fed to twoparallel op-amps U4 and U3 to implement the boundaries. By using afeedback circuit, discrepancies between desired current and actualcurrents can be resolved and converged.

Alternatively, the duty-cycle boundaries may be implemented withsoftware and digital converters. Software may be limited because ofsampling rates. Nevertheless, if a controller can be configured as such,it may be more advantageous because of price savings associated withsoftware.

In FIG. 9, the op-amps serve as clamps, where the lower op-amp lets anerror pass though unless it is negative, in which case the error is setto negative 0.5 amps. The top op-amp may be providing the top boundary.ILTR+ and ILTR− provide signals that represent the top and bottomboundaries. These signals may be sent to op-amps U5 and U7. Thus, thefeedback controller is an extension of the duty-cycle boundary featuresand may or may not be used in embodiments.

FIG. 10 shows a power circuit inverter including a feedback circuit asmay also be used in embodiments. This power circuit includes high-sideswitches 1110 and 1014, low side switches 1012 and 1016, seriesinductors 1020 and 1021, capacitor 1070 and split phase voltage system1081 and 1082. Also shown in FIG. 10 are low-side bus reference senseresistors 1050 and 1051. By using these sense resistors current may besensed from the common of the DC supply rather than or in addition tosensing form the filter inductors as discussed above. By placing thesensors on the low side of the DC supply, control circuitry may bereferenced from the bus. Comparatively, if current is sensed from thefilter inductors then high-side or floating sense resistors arepreferably used. In embodiments, low-side sensing may be preferred ashigh side sensing may invoke unwanted noise or require costly componentsto avoid, especially when small amounts of voltage, on the order of 20mV or so are provided by the high-side sense resistors from the nodethat oscillates in the range of 0 VDC to 400 V DC. Nevertheless,embodiments may include high-side buses in their designs. Thus, low-sidebus reference sensing may be preferred in embodiments.

The use of sense resistors 1050 and 1051 in each of the MOSFET legs ofthe dc-ac output stage of FIG. 10 shows that embodiments may includethese low-side sense resisters when a common is readily accessible nearthe switches. As noted, the inductors 1020 and 1022 of the embodiment ofFIG. 10 are effectively in series and are coupled to a split-phasevoltage system 1081 and 1082. For purposes of circuit analysis, thissplit-phase system may be considered a single source of double thevoltage value.

FIG. 11 shows that the low-side sense resistor signals may be amplifiedand multiplexed so as to create a signal i_(sns) representing theabsolute value of the line current. This signal may then be comparedwith a commanded boundary current to control switching logic of theswitches. The circuit of FIG. 12 shows one such circuit as to how thei_(sns) signal may be used in controlling switching logic.

In FIG. 11, two differential amplifiers 113 and 1140 are shown andcoupled to provide gain to the small sense resistor voltages of senseresisters 1050 and 1051. These sense resistors, i.e., leg resistors, areshown and may be referenced to the bus common. The differentialamplifier output may be multiplexed by the analog switch/multiplexer1110, which is shown toggling between two outputs. The multiplexing maybe controlled by logic signals P 1120 and P 1121. As shown, this controland multiplexing produces an i_(sns) value 1130 that represents theabsolute value of the line current in the switching block. In use, witha positive current at switch 1016, a proportional voltage may beproduced across sensor 1051. This voltage may then be referenced into anapplicable current. By alternating between leg resistors 1050 and 1051the current in the switch block can be synthesized.

FIG. 12 shows embodiments for making the comparison to generate the sameswitching signals. FIG. 12 uses a set reset flip flop with a truthtable. Shown in FIG. 12 is that the sensed current may be shifted up inembodiments (0.5 as shown in this figure) to account for the lower bound(in this circuit, the sensed current +0.5 is compared to zero volts).The upper bound then also has to be shifted by +0.5 to account for thenegative lower bound, and then another 0.5 to account for the shift inthe sensed value. The comparators produce the switching signal which isset by the SR flip-flop. The switch logic device 1220 may then producethe appropriate switch gating signals consistent with the truth tableshown.

FIG. 12 provides a circuit topology showing how a sensed current i_(sns)may be compared to a command current in order to control switch blocklogic in embodiments. The sensed current i_(sns) may originate incircuits similar to those shown above as well as in other circuittopologies. In the topology of FIG. 12, digital to analog converter 1250may receive a signal from the processor and blocks. This signal mayrepresent the command current 1290, which is shown as 2i*|1. Thiscommand current may be fed to comparator 1270, which may also receive asensed current signal i_(sns). This sensed current signal may beincreased and may be offset by 0.5 to accommodate and provide for thebody drain discussed above. The i_(sns) signal may also be fed intocomparator 1271 in order to be compared to ground. The outputs of thecomparators 1270 and 1271 may be fed to the set-reset flip flop 1230.This flip flop may itself be coupled to a switch logic device 1220,which also has logic signal P as an input. The switch logic device maygenerate output drive signals for switches q_(oc1)-q_(oc4) dependingupon the logic state of P and Q. The flip flop truth table 1240 providesthe logical output forth e logic device 1220 depending upon the inputs.

In operation, when the comparators detect that the command currentthreshold or the low side thresholds are crossed, signals may be sent tothe SR flip flop 1230 to provide the needed logic for controlling theswitches by the switch logic device. As upper threshold are met,alternate switches may be thrown to reverse the current and maintain itwithin the thresholds. Likewise, when the bottom threshold is met, theswitch logic may be reversed such that current will rise against towardsthe upper threshold. This containment between the thresholds, while alsocrossing a zero-volt setting can serve to reduce body diode losses.Still further, in embodiments, rather than using a fixed 0.5 adjustmentto the i_(sns) current, a variable benchmark may be used as well. Thisvariable benchmark may serve to smooth zero-transition noise as thecurrent and voltage cycle from positive to negative.

In further embodiments, the boundary references, comparison, andsubsequent gating control may also be performed by software. Thesoftware may sample the applicable voltage sensor, determine theapplicable current, compare that current to a threshold and generatesignal for use by a switching gating control. When sampling rates arehigh, software may not be preferred as it may not be able to rendersignals at that speed. However, when cycle rates are lower, softwarecomparators may be preferred to simplify the circuit design.

FIG. 13 provides features or processes as may be employed withembodiments. These features and processes may be employed as describedand in variants as well. The features and processes may be performed inthe presented order, in different orders, and with more or less than thefeatures and processes provided. In other words, some features orprocesses may be added and others may be skipped or used elsewhere inembodiments.

As can be seen in FIG. 13, embodiments may include generating a commandsignal for use in instructing or controlling inverter switch control.The inverter switch control may be consistent with discussions above,including using the logic tables provided in FIG. 12 and implicitlyprovided in FIG. 3.

As can also be seen in FIG. 13, a process in embodiments may alsoinclude generating a sensed current signal as shown at 1320,establishing an upper voltage boundary, as shown at 1330, andestablishing a lower voltage boundary, as shown at 1340. Consistent withdiscussions above, the upper voltage boundary may be a constant value ora variable value. Likewise, the lower voltage boundary may also be aconstant value or a variable value.

As shown in FIG. 4, as current alternates back and forth, the upper andlower voltage boundaries may switch from being a variable threshold tobeing a constant threshold. The variables used for these duty-cycleboundaries, may include the formulas identified and described above. Forexample, these can include the formulas shown in FIG. 7, as well asthose identified in the text above. Other formulas may also be used.

In embodiments, as shown in FIG. 13, the lower voltage boundary may beoffset such that it falls below are becomes negative for approximatelyhalf a cycle. This offset may be a constant, as well as a variable. Inpreferred embodiments the offset will be a constant value. Likewise, theupper value may also be offset opposite to and in response to the offsetfor the lower boundary. By creating equal and opposite duty-cycleboundary offsets the output currents can remain within expected values.

As explained at 1350, because the current is swinging between positiveand negative values, the offsets may be considered to apply within eachcycle. In other words when the measure voltage of a car is negative, thelower boundary may be a constant, and may be offset by another constantvalue. Conversely, when the voltage swings positive and the current isnegative, that upper boundary may now be considered to be a constant andthe offset also a constant value. In embodiments the absolute values maybe considered when determining and establishing offsets.

As explained above, the offsets and the boundaries may be set such thatinverter switching losses may be minimized. In embodiments, residentvoltage charges associated with reverse recovery charges, may dissipateor be reduced through the introduction of switching delays, and/orthrough the use of certain switch timing.

As shown at 1370, the sensed current signal may then be compared to theestablished voltage boundaries when the upper boundary is applicable,and to an established lower boundary, when the lower boundariesapplicable. This determination is shown at 1380.

As shown at 1390, if the determination reveals that the signal fallswithin the applicable boundary, then one or more powertrain switches maybe triggered in the circuit. Conversely, if the sensed current signalfalls outside of the applicable boundary, then no triggering signals forthe MOSFET or other powertrain switches may be sent. As shown in FIG.13, the process may begin again at 1310 or remain in a sensing loop at1395. Embodiments may contain other steps or features as well.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specific thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operation, elements,components, and/or groups thereof.

Embodiments may be implemented as a computer process, a computing systemor as an article of manufacture such as a computer program product ofcomputer readable media. The computer program product may be a computerstorage medium readable by a computer system and encoding a computerprogram instructions for executing a computer process.

The corresponding structures, material, acts, and equivalents of allmeans or steps plus function elements in the claims below are intendedto include any structure, material or act for performing the function incombination with other claimed elements are specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill without departingfrom the scope and spirit of the invention. The embodiment was chosenand described in order to best explain the principles of the inventionand the practical application, and to enable others of ordinary skill inthe art to understand the invention for embodiments with variousmodifications as are suited to the particular use contemplated.

1. A power converter comprising: a switching circuit, the switchingcircuit having a first switch with an associated antiparallel diode, asecond switch with an associated antiparallel diode, a third switch withan associated antiparallel diode, and a fourth switch with an associatedantiparallel diode, the first switch, the second switch, the thirdswitch, and the fourth switch, configured to be electrically coupled toa direct current source, the first switch, the second switch, the thirdswitch, and the fourth switch operable to be selectively switched on andoff in order to send current, from a direct current source, in analternating fashion, to a load, and; a comparator circuit, thecomparator circuit configured to receive a first signal, the firstsignal representing the value of current flowing from the switchingcircuit, the comparator circuit configured to receive a second signal,the second signal representing a variable commanded current from theswitching circuit; the comparator circuit configured to compare thefirst signal and the second signal and output an indicator representingwhether the first signal has exceeded the value of the second signal; aswitch logic device configured to receive input from the comparatorcircuit and a logic signal, and to send gate drive signals to each ofthe four switches, wherein the variable commanded current defines aduty-cycle boundary that introduces delay in switching a switch in theswitching circuit for a duration that provides for the dissipation ofcharge in the antiparallel diode associated with the switch beingswitched, before the switch is switched.
 2. The power converter of claim1 wherein the introduced delay in switching includes sending switchingsignals to the first switch and the second switch to alternately switchon and off while also sending signals to the third switch toindependently switch on and off and while sending signals to the fourthswitch to hold the fourth switch open.
 3. The power converter of claim 2wherein the first switch is turned off and the second switch is turnedon when the comparator circuit output indicates that the first signalhas crossed the value of the second signal.
 4. The power converter ofclaim 2 wherein the introduced delay in switching also includes sendingswitching signals to the third switch and the fourth switch toalternately switch on and off while also sending signals to the firstswitch to independently switch on and off and while sending signals tothe second switch to hold the second switch open.
 5. The power converterof claim 4 wherein the third switch is turned off and the fourth switchis turned on when the comparator circuit output indicates that the firstsignal has crossed the value of the second signal.
 6. The powerconverter of claim 5 wherein the value of the second signal is negative.7. The power converter of claim 1 wherein one or more switches is aninsulated gate bipolar transistor.
 8. The power converter of claim 1wherein one or more switches is a metal-oxide-semiconductor field-effecttransistor.
 9. The power converter of claim 1 wherein the switch logicdevice is further configured to send gate drive signals to each of thefour switches to concurrently pulse each switch at an anticipated zerocurrent crossing.
 10. The power converter of claim 9 wherein the pulseof each switch has a duration of substantially 200 microseconds or more.11. An inverter circuit comprising: an H-bridge switching circuitemploying transistors; a sensor circuit configured to provide a sensorsignal indicative of current flowing from the H-bridge switchingcircuit; a comparator circuit, the comparator circuit configured toreceive the sensor signal from the sensor circuit, and compare thesensor signal to an upper boundary and a lower boundary, the upperboundary being variable during the first half of a current cycle and thelower boundary being variable or fixed during the first half of acurrent cycle, the comparator circuit further configured to generate acontrol signal indicating whether the sensor signal crossed the upperboundary or the lower boundary; and a logic circuit electrically coupledto the H-bridge switching circuit, the logic circuit configured to sendswitching instructions for switching switches in the H-bridge when thecomparator control signal indicates that the sensor signal has notcrossed the upper boundary or the lower boundary, the logic circuitswitching instructions including signals that alternately switch a pairof transistors in the H-bridge on and off, independently switch a thirdtransistor in the H-bridge on and off, and hold open a fourth transistorin the H-bridge.
 12. The inverter circuit of claim 11 wherein the upperboundary is defined by voltage/amps plus a constant.
 13. The invertercircuit of claim 11 wherein the lower boundary is offset from zerocurrent and is a negative value during the first half of a currentcycle.
 14. The inverter of circuit claim 11 wherein the sensor circuitincludes a low-side common bus sense resistor.
 15. The inverter circuitof claim 11 wherein the logic circuit is coupled to a set-reset flipflop receiving signals from the comparator circuit and wherein the logiccircuit is configured to receive a logic signal indicating the directionof sensed current.
 16. The inverter circuit of claim 11 furthercomprising: a digital to analog converter, the digital to analogconverter coupled to the comparator circuit, the digital to analogconverter configured to receive a digital input signal representingcommanded current and to convert that digital signal to an analog signalrepresenting commanded current, the analog signal output to thecomparator circuit; and wherein the H-bridge switching circuit includesa plurality of antiparallel diodes, wherein antiparallel diodes areassociated with transistors of the H-bridge circuit.
 17. The invertercircuit of claim 11, wherein the H-bridge circuit includesmetal-oxide-semiconductor field-effect transistors.
 18. (canceled)
 19. Amethod for converting direct current to alternating current, the methodcomprising: generating a command signal representing a desired current;sensing an existing current in an H-bridge switch powertrain, thepowertrain having first through fourth switches; comparing the commandsignal with the sensed current; and generating a first set of switchingsignals, the set including signals to: alternately switch a first switchand a second switch in the H-bridge powertrain on and off, independentlyturn a third switch in the H-bridge powertrain on and off, and hold afourth switch of the H-bridge powertrain open.
 20. The method of claim19 further comprising: generating a second set of switching signals, thesecond set of switching signals including signals to alternately switchthe third and fourth switches of the H-bridge powertrain on and off;independently turn the second switch in the H-bridge powertrain on andoff; and hold the first switch in the H-bridge powertrain open.
 21. Themethod of claim 19 further comprising: pulsing each of the four switchesof the H-bridge for a duration of time when the sensed current flow isanticipated to be zero, representing a change in direction of currentflow.
 22. A power converter comprising: a step-down converter circuit ofswitching type having an input port to couple to a supply voltage andhaving an output port to provide an output voltage at a magnitude thatis lower than a magnitude of the supply voltage; a control circuitconfigured to receive a feedback signal and regulate the magnitude ofthe output voltage in response thereto; a DC/AC converter circuit ofswitching type having a primary side and a secondary side, the primaryside having an input port coupled to the output port of the step-downconverter circuit, the secondary side having an output port to providean AC output voltage; a rectifier circuit having an input port and anoutput port, the input port being coupled to the secondary side of theDC/AC converter circuit, the output port supplying a DC voltage; and afeedback circuit to generate the feedback signal in response to theoutput port of the rectifier circuit.